The present invention relates to the field of semiconductor devices and their manufacture. More specifically, in one embodiment the invention teaches the selective implantation of p-type dopants such as boron to improve the performance of bipolar junction transistors ("BJTs").
BJTs and their fabrication on semiconductor wafers are known. In order to fabricate BJTs with reduced size, it is often desirable to fabricate such transistors with a walled emitter. A "walled emitter" BJT is a BJT in which the emitter of the transistor intersects the isolation oxide. Transistors with walled emitters generally require reduced amounts of layout area per transistor. For comparison, in a non-walled emitter BJT, the emitter is separated from the isolation oxide, the resultant structure having a generally uniform emitter-base edge profile on all edges. This type of transistor usually requires more layout area for a given lithography technique than a walled emitter BJT.
Walled emitters have several disadvantages, among which are collector-emitter leakage currents ("I.sub.CEO ") at the edges of the walled emitter. I.sub.CEO is the current which flows between the collector and emitter when the base terminal of the transistor is not biased at a given collector-emitter voltage. I.sub.CEO is generally measured when the collector-emitter voltage is maintained within the normal operating region, not when the transistor is operated at the breakdown voltage, and I.sub.CEO is ideally zero.
I.sub.CEO can be non-zero due to a number of factors. The walled emitter edge can be reduced in base width and/or mobile charge carrier concentration due to intrinsic base boron segregation into the field oxide. This reduction in base width can increase I.sub.CEO.
Oxide charges present in the field oxide region can also cause an inversion of the P-type intrinsic base region at the edge of the walled emitter, decreasing the base width and/or mobile charge carrier concentration This also results in an increase in I.sub.CEO.
Base width can also be reduced at the edge of the walled emitter edge where the devices have been fabricated with implanted, diffused and polysilicon emitter devices. In such devices, if the isolation oxide window is larger than the window that defined the intrinsic base region, the oxide can etch and enlarge the active window between the base and the emitter
The known methods for reducing or controlling I.sub.CEO leakage in walled emitters has generally tended to reduce the performance of the BJTs.
For example, increasing the base width or increasing the mobile charge carrier concentration in the base region both reduce the performance of the BJT by increasing the transit time of charges in the base region and by increasing the parasitic capacitances of the BJTs.
The use of a high energy, low dose secondary base implant that penetrates the "bird's beak" at the edge of the isolation zone, and which increases the base width and charge at the edge of the walled emitter is also known. Unfortunately, this method increases both the base junction depth of the device and the electrical signal transit time for the transistor while increasing parasitic capacitances.
It would be of significant advantage if a new method for controlling I.sub.CEO currents in a BJT having a walled emitter could be developed without the performance penalties of the known art.